Rf and if digitization in Radio Receivers: Theory, Concepts, and Examples

 

18 

Subranging ADCs are becoming very popular since they can achieve high-speed operation with 

high resolution. They require far fewer comparators for a given resolution than flash ADCs. 

While the internal ADCs within a subranging ADC have traditionally been flash ADCs, other 

types of ADCs may be used. For example, a new architecture, the cascaded magnitude amplifier, 

has been used in the Analog Devices AD9042 (a 12-bit, 41-Msamples/s subranging ADC). This 

architecture provides a very high-speed conversion and greatly reduces the number of 

comparators required in the internal ADCs.  

The cascaded magnitude amplifier (MA) ADC consists of B−1 MAs in series and a single 

comparator placed in series after the last MA. A diagram showing the operation of the cascaded 

MA ADC is given in Figure 7. Referring to this figure, the first MA compares the input signal to 

a voltage level V

fs

/2 where V

fs

 is the full-scale input voltage of the ADC. If the input signal is 

greater than V

fs

/2, the bit representing this MA is set to 1. If the input signal is less than V

fs

/2, the 

bit representing this MA is set to 0. Therefore, this first MA divides the full-scale voltage into 

two regions and the bit representing this MA is set according to the region in which the input 

voltage falls. 

The next (second) MA uses the output of the first MA as its input. As shown in Figure 7, the 

second MA divides each of the two regions defined by the first MA into two additional regions. 

If the input voltage to the first MA is between V

fs

 and V

fs

/2, the second MA determines if the 

input signal is between V

fs

 and 3V

fs

/4 or between 3V

fs

/4 and V

fs

/2. The bit representing this MA 

then is set to 1 or 0, respectively. Conversely, if the input voltage to the first MA is between 0 

and V

fs

/2, the second MA determines if the input signal is between V

fs

/2 and V

fs

/4 or between 

V

fs

/4 and 0. The bit representing this MA then is set to 0 or 1, respectively.  

Each subsequent MA (and the final comparator) further subdivides the regions in a similar 

manner, providing all of the necessary quantization levels (Figure 7 shows operation up to the 

third MA). Because of the way that the bit representing an MA is set (as seen in Figure 7), the 

output bits from each MA form a Gray code that represents the input signal voltage. In the Gray 

code, only one bit changes in the code word from one quantization level to another. 

Determination of the output bits is dependent upon the input signal propagating through the 

cascaded MAs only. Very high-speed operation is achieved because the response time of the 

amplifiers is very fast.  

 

19 

 

Figure 7. Operation of the cascaded magnitude amplifier ADC. 

7V

fs 

8 

3V

fs 

4 

V

fs

 

5V

fs

 

8 

V

fs 

2 

3V

fs 

8 

V

fs 

4 

V

fs 

2 

V

fs 

8 

V

fs

 

4 

MA3 

3V

fs 

4 

V

fs

 

V

fs 

4 

0 

V

fs 

2 

MA2 

bit = 1 

bit = 0 

bit = 0 

bit = 1 

bit = 1 

bit = 0 

bit = 0 

bit = 1 

bit = 1 

bit = 0 

bit = 1 

bit = 0 

0 

V

fs 

2 

0 

V

fs

 

 

bit = 1 

bit = 0 

MA1 

MA1 = First Magnitude Amplifier 

MA2 = Second Magnitude Amplifier 

MA3 = Third Magnitude Amplifier 

 

V

fs 

2 

3V

fs 

4 

 

20 

Integrating ADCs are another category of converters. They convert the analog input signal 

amplitude into a time interval that is measured subsequently. The most popular methods within 

this category of ADCs are the dual slope and charge balancing methods. While these types of 

ADCs are highly linear and are good at rejecting input noise, they are quite slow.  

A relatively new type of ADC is the ΣΔ converter. The first-order ΣΔ converter is the most basic 

ΣΔ converter (Figure 8). It consists of a ΣΔ modulator, a digital filter, and a decimator. To 

understand how this converter works, an understanding of oversampling, noise shaping, digital 

filtering, and decimation is required.  

 

Figure 8. First-order ΣΔ ADC. 

The operation of the ΣΔ converter relies upon the effects of oversampling. ΣΔ converters use a 

very low-resolution quantizer (typically a 1-bit quantizer) and sample at a rate much greater than 

2f

tải về 0.99 Mb.

Chia sẻ với bạn bè của bạn: