Rf and if digitization in Radio Receivers: Theory, Concepts, and Examples
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| X(s) and not the quantization noise. For high frequencies (s » 1), Y(s) is primarily a function of
the quantization noise [18]. More than one integration and summing stage can be used in the modulator to provide even more noise shaping. Third and even higher-order ΣΔ converters have been designed. (The number of integrators determines the order of the modulator.) Higher-order modulators further decrease the amount of quantization noise in the desired signal’s band by placing more of the quantization noise above f
. Therefore, higher-order ΣΔ converters can provide the same apparent resolution with less oversampling than lower-order ΣΔ converters [19]. ΣΔ modulators higher than second- order provide some difficult design challenges. Instability becomes possible and must be considered carefully in the design. After the ΣΔ modulator, a digital filter is used. This digital filter is used to 1) filter the quantization noise above f
and 2) prevent aliasing when the signal is decimated. Decimation is a process of reducing the data rate by resampling a discrete-time signal at a lower rate. Decimation is useful in ΣΔ converters because the oversampling creates a data rate that is much higher than 2f
. After filtering the quantization noise, the highest frequency component of the desired signal is only f
. Therefore, the required sampling rate only needs to be 2f max to fully reconstruct the desired input signal. Decimation is performed by saving only one out of every M samples to reduce the data rate to (or a little higher than) 2f max .
Decimation may be combined with digital filtering for more efficient processing. FIR filters can be used to provide both filtering and decimation at the same time. This is true because the FIR filter output needs to be computed for only one out of every M input samples. Conversely, infinite impulse response (IIR) filters cannot be used for decimation because they rely on all of the input samples to produce the proper output. IIR filtering, if desired, can be performed after decimation. The ΣΔ converters described are designed to operate on baseband signals. A new type of converter, the bandpass ΣΔ converter, shows great potential for radio receiver applications for digitization at the RF or IF. This converter architecture is identical to the traditional ΣΔ converter except that the integrators are replaced by bandpass filters and a bandpass digital filter after the ΣΔ modulator is used. Use of bandpass filters instead of integrators shapes the quantization noise such that it is moved both below and above the desired band of frequencies. This provides a bandpass region of low quantization noise. Bandpass ΣΔ converters are currently a very promising research and development topic. H(s) X(s)
Q = Quantization Noise + − Y(s) Amp
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The ΣΔ converter has a couple of advantages over the more traditional types of ADCs. Because of the high sampling rate, the attenuation requirements on the anti-aliasing filter can be lessened. Additionally, an improvement in the linearity of the ADC results in an improved SFDR. This advantage results from using a 1-bit or other low-resolution quantizer. One disadvantage of ΣΔ converters that are currently available is that they typically are limited to signal bandwidths below 150 kHz (for a 12-bit ENOB). The design of high-speed ADCs usually incorporates both a sample-and-hold amplifier (SHA) and a quantizer. Many ADCs provide a SHA as an integral part of the ADC. External SHAs also can be used with ADCs but this requires careful design considerations of the SHA and ADC specifications, in addition to timing and interface issues between the external SHA and the ADC. The purpose of the SHA in ADC applications is to keep the input signal constant during the ADC conversion. While there are many different SHA implementations, all SHAs consist of four basic components: an input amplifier, capacitor, output buffer, and switching circuit. An example SHA showing the basic components is given in Figure 11. The input amplifier provides a high input impedance to the input signal and supplies the necessary current to charge the hold capacitor. When the switch closes, the SHA operates in the track mode and the voltage on the hold capacitor follows the input signal. When the switch opens, the SHA operates in the hold mode. Ideally, the voltage on the hold capacitor remains at its value before the switch opened. Since it has a high input impedance, the output buffer prevents the hold capacitor from discharging significantly. The hold command controls the operation of the switch and determines when the SHA is in the track or hold mode [20].
Figure 11. Example showing the basic components of a sample-and-hold circuit. Sometimes SHAs are called track-and-hold amplifiers (THAs). The name used depends on how the device is used. When the device spends most of its time in the hold mode and just a short time in track mode (enough time to take a sample of the input), the device is called a SHA. When the device spends only a short time in the hold mode and most of its time in the track mode, it is called a THA [21]. For radio receiver applications, typically high-speed ADCs are required, especially for direct digitization of the RF or digitization of wideband IF. Because of this, successive-approximation, subranging, flash, and bandpass ΣΔ ADCs are the most likely types of ADCs to be used for these applications. Input
Amp Buffer
Output Switch
Driver Hold
Command Hold
Capacitor |