ADC Performance vs. Sampling Rate

The performance of ADCs continues to improve at a rapid rate. For radio receiver applications 

using digitization at the RF or IF, ADCs with both high sampling rates and high performance are 

desired. Unfortunately, there is a tradeoff between these two requirements. As a general trend, 

although not always true, the higher the performance of the ADC, the lower its maximum 

sampling rate will be. The goal of direct digitization at the RF in radio receivers at increasingly 

higher frequencies and wider bandwidths is one of the forces driving the development of higher-

performance, faster ADCs. Digital sampling oscilloscopes are another example of applications 

that encourage the development of higher-performance, faster ADCs.  

Interleaving is a common technique used to increase the sampling rate beyond the capability of a 

single ADC. In this technique, multiple ADCs of the same type are staggered in time to achieve 

higher sampling rates. Each ADC is offset in time from the preceding ADC. For uniform sample 

spacing, this offset is determined by dividing the time interval between samples of a single ADC 

by the total number of ADCs to be used. The interleaving technique is used extensively in digital 

sampling oscilloscopes. 

Examples of current high-speed ADC technology showing maximum sampling rates for various 

ADC resolutions are given in Table 2. The low-resolution (6- or 8-bit), high sampling rate ADCs 

are typically implemented as flash ADCs and therefore are limited in SFDR.  

When selecting an ADC for a specific radio receiver application, in addition to the sampling rate, 

one must consider critical specifications that characterize the ADC performance such as the 

SNR, SFDR, NPR, and full-power analog input bandwidth. In certain applications such as 

channelized PCS and mobile cellular systems, instead of digitizing the entire band with a single 

high-speed ADC, parallel ADCs used to digitize narrower bandwidths are often practical ADC 

architectures. In this case, ADCs with better performance can be used since the demands of a 

high sampling rate are relieved.  

Table 2. Examples of Current High-Speed ADC Technology 

Resolution 

(Number of Bits) 

Sampling Rate 

(Msamples/s) 

Manufacturer 

6 

4000 

8 

1000 

8 

2000* 

8 

3000 

10 

Pentek 

50 

 

26 

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