Rf and if digitization in Radio Receivers: Theory, Concepts, and Examples



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2.4  ADC Conversion Methods  

Many methods for implementing ADCs currently exist. Several of the most common techniques 

are presented below. The counter ADC uses a digital-to-analog converter (DAC) and increases 

the output of this DAC one quantization level at a time using a counter circuit until the output of 




 

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the DAC equals the amplitude of the analog signal at a given time. The output of the counter 

then provides the digital representation of the analog input voltage. A major drawback to this 

type of converter is that it is fairly slow. An improvement to the counter type ADC is the 

tracking ADC. This type of converter is similar to the counter ADC except that an up-down 

counter is used in place of the ordinary counter. In this ADC, the output of the internal DAC is 

compared to the analog input signal. If the amplitude of the analog input signal is greater than the 

output of the DAC, the counter counts up; if it is less than the output of the DAC, the counter 

counts down. The tracking ADC is much faster than the counter ADC when there are only small 

changes in the amplitude of the input signal. For large changes in the input signal amplitude this 

type of ADC is still fairly slow.  

The counter and tracking ADCs belong to the feedback class of ADCs. The successive-

approximation ADC also belongs to this class. This type of ADC again uses a DAC in a 

feedback loop. For a conversion with this ADC, a register is used to set the most significant bit 

(MSB) in the DAC to 1. The output of the DAC is compared to the amplitude of the analog 

input. If the DAC output is greater than the analog input, the MSB of the DAC is cleared

otherwise it is kept set to 1. The next significant bit of the DAC is then set to 1 and the output of 

the DAC again is compared to the amplitude of the analog input. If the DAC output is greater 

than the analog input, this bit is cleared. This process continues for all B bits of the DAC. The 

input of the DAC provides the output of the ADC. The conversion is made in B steps making this 

technique quite efficient and hence reasonably fast. Successive-approximation is one of the most 

popular ADC techniques.  

The parallel or flash ADC is used for applications that require the fastest possible digitization. In 

the current state-of-the-art technology, sampling rates on the order of 500-1000 Msamples/s for 

an 8-bit ADC most likely imply that a flash ADC is being used. This type of converter uses a 

bank of 2

B

 − 1 voltage comparators in parallel where B is the number of bits of the ADC. The 

analog input signal is applied to one input on all of the voltage comparators while the other input 

to each comparator is a reference voltage corresponding to each of the 2



B

 − 1 quantization levels. 

The reference voltages typically are generated by a voltage divider network. All comparators 

with reference voltages below the analog input signal produce a logical 1 output. The remaining 

comparators, with reference voltages equal to or above the input signal, produce a logical 0 

output. The outputs of the comparators are then combined in a fast decoder circuit to generate the 

output digital word of the ADC. Therefore, conversion takes place in only two steps (voltage 

comparison and decoding), making this technique the fastest of the commonly available 

techniques. A major limitation of this type of ADC is the large number of comparators required 

in the implementation. For a B-bit flash ADC, 2



B

 − 1 comparators are needed. Since an 8-bit 

ADC requires 255 comparators and a 9-bit ADC requires 511 comparators, flash ADCs of more 

than 8 bits typically are not available commercially. Linearity is a problem in flash ADCs as 

observed in degraded SFDR performance.  

One technique used to implement high-speed ADCs combines two separate B-bit ADCs (usually 

flash ADCs) to produce a single ADC with a resolution of 2B bits. For example, two 4-bit 

converters can be combined to provide an 8-bit converter. In this technique, the first 4-bit ADC 

digitizes the analog input. The output of the ADC is then converted back into an analog signal 

using a DAC. This signal then is subtracted from the original input analog signal producing a 

difference signal. This difference signal is then amplified and digitized using the second 4-bit 



 

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ADC. The amplifier gain is set to provide a full-scale input signal into the second ADC. The 

outputs of both 4-bit ADCs then are combined using digital error correction logic to produce an 

8-bit output representing the analog input signal [17]. This type of ADC is called a two-stage 

subranging ADC. Subranging ADCs with up to five stages are available. Signal delays 

(sometimes called pipeline delays) increase with each additional stage and must be considered in 

the design of subranging ADCs. Subranging ADCs exhibit a repetitive nonlinearity due to the 

nature of digitizing difference signals. This is visualized best by considering a ramp input into an 

ideal ADC representing the first stage of a subranging ADC. The transfer function of the ideal 

ADC is shown in Figure 6(a) while the ramp input is shown in Figure 6(b). The output of the 

first ADC is a quantized version of the ramp as shown in Figure 6(c). Subtracting a reconstructed 

version of the input ramp from the quantized version, produces a repetitive ramp difference 

waveform that repeats 2




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