Postdigitization Algorithms for Improving Spurious Free Dynamic Range

As previously mentioned, there are numerous postdigitization techniques for optimizing the 

quantization process. Many of these techniques are used to increase the SNR of the quantizer by 

improving the predictor characteristics of differential quantization schemes. Another area of 

postdigitization processing provides compensation for the nonlinearities that occur in practical 

implementations of ADCs. As discussed in Section 2 of this report, these nonlinearities produce 

spurious signals that can reduce significantly the SFDR of the ADC. The purpose of this 

compensation is to suppress the spurious responses below the noise in the frequency band from 0 

to f

s

/2. Two of these techniques, phase-plane and state variable compensation, are discussed 

below [13], [14].  

Both techniques are used to identify a set of correction factors that can be used to compensate for 

any nonlinearity throughout the full amplitude range of the ADC. In phase-plane compensation, 

the procedure for correcting the digitized signal is as follows: The input signal is split into two 

separate signals. One signal is fed into the ADC and the other is sent through an analog 

differentiator and then digitized by a second ADC. The differentiated signal is used to determine 

the instantaneous slope of the signal. The output of both ADCs then is used to determine the 

correction factor to be applied to the ADC output representing the digitized input signal. A table 

consisting of correction factors for each possible combination of quantization level and 

instantaneous slope is developed for an individual ADC based on measurements of that 

particular ADC. This table then is stored in RAM and is used to provide the correct ADC output 

for any given input signal amplitude. Studies using this technique show as much as a 15- to 16-

dB (about 2.5 bits) improvement in the SFDR over uncompensated ADCs [14]. This 

improvement, however, is restricted to a narrow frequency band well below f

/2. 

/2 frequency band, a state 

variable compensation technique was also proposed. This type of compensation is implemented 

by applying the input signal to an ADC and splitting the output of the ADC into two signals. One 

of these signals is used without modification while the other is delayed by a single clock cycle 

(one sample of the input signal). The two outputs, representing the quantization levels for the 

present and previous ADC outputs, then are used to determine the correction factor to be applied 

to the present ADC output. A table of correction factors for each possible combination of present 

and previous quantization levels is developed for an individual ADC based on measurements of 

that particular ADC. As in phase-plane compensation, this table is stored in RAM and is used to 

provide the correct ADC output for any given input signal amplitude. Tests using this technique 

also show as much as a 16-dB improvement in the SFDR over the entire 0 to f

/2 frequency band 

for the particular sampling rate.  

While compensation techniques require additional hardware and testing of individual ADCs, 

they can improve the SFDR of the ADC significantly without increasing its resolution (number 

of bits). In essence, they bring the characteristics of the ADC closer to the theoretical expectation 

 

37 

of its performance. An underlying assumption in these techniques, however, is that the ADC 

characteristics are static. Testing of ADCs has shown that for most ADCs this is a valid 

assumption [14].  

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