Paging (3) - Figure 3-10. The internal operation of the MMU with 16 4-KB pages.
- Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
- Figure 3-11. A typical page table entry.
- Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
Speeding Up Paging - Major issues faced:
- The mapping from virtual address to physical address must be fast.
- If the virtual address space is large, the page table will be large.
- Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
Translation Lookaside Buffers - Figure 3-12. A TLB to speed up paging.
- Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
- Figure 3-13. (a) A 32-bit address with two page table fields. (b) Two-level page tables.
- Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
Inverted Page Tables - Figure 3-14. Comparison of a traditional page table with an inverted page table.
- Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
- Tanenbaum & Bos, Modern Operating Systems: 4th ed., Global Edition (c) 2015 Pearson Education Limited. All rights reserved.
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