Recommendation G.957 (06/99)
24
T1509060-92
H
D
Fibre distance
R
e
fl
ect
ed
p
o
w
e
r
(In time)
Figure I.2/G.957 – OTDR trace at a discrete reflector
APPENDIX II
Implementation of the Consecutive Identical Digit (CID) immunity measurement
II.1 Introduction
STM-N signals contain regions within the data stream where the possibility of bit errors being
introduced is greater due to the structure of the data within these regions.
Three cases in particular may be identified:
1)
errors resulting from eye-closure due to the tendency for the mean level of the signal within
the equipment to vary with pattern-density due to alternative current couplings ("DC
wander");
2)
errors due to failure of the timing recovery circuit to bridge regions of data containing very
little timing information in
the form of data transitions;
3)
errors due to failure of the timing recovery circuit as in 2) above but compounded by the
occurrence of the first row of the STM-N section overhead bytes
preceding a period of low
timing content (these bytes have low data content, particularly for large N).
In order to verify the ability of STM-N equipment to operate error-free
under the above conditions, a
possible method to assess the consecutive identical digit (CID) immunity of a circuit block is
presented.
This method may be employed during the design phase of the equipment and appropriate points in
the production assembly process.
Alternating digital signal patterns may be used to verify the adequacy of timing-recovery and
low-frequency performance of STM-N equipments.
Appropriate pattern sequences are defined below and in Figure II.1.
This test does not attempt to simulate conditions which may occur
under anomalous operating
conditions to which the equipment may be subjected.
