Itu-t rec. G. 957 (06/99) Optical interfaces for equipments and systems relating to the synchronous digital hierarchy
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- Figure II.1/G.957 – STM-N pattern dependence test sequence II.2 Method
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Recommendation G.957 (06/99) 25 Nx 10101010 B T1509200-92 NxA1 NxA1 NxA1 NxA2 NxC1 X NxA2 NxA2 X Nx 10101010 D A B D C D A All 1’s Pseudorandom. 1/2 All 0’s Pseudorandom. 1/2 1 test period Figure II.1/G.957 – STM-N pattern dependence test sequence II.2 Method The specific test patterns are made up of consecutive blocks of data of four types: a) all ones (zero timing content, high average signal amplitude); b) pseudo-random data with a mark-density ratio of 1/2; c) all zeros (zero timing content, low average signal amplitude); d) a data block consisting of the first row of section overhead bytes for the STM-N system under test. The test pattern is shown in Figure II.1 where the regions A, B, C and D are identified. The duration of the zero-timing-content periods A and C is made equal to the longest like-element sequences expected in the STM-N signal. A value of nine bytes (72 bits) is provisionally proposed for this. The duration of the pseudo-random periods should allow recovery of both the zero base line offset of the signal and of the timing recovery circuit following occurrence of the A and C periods. Therefore it should be longer than the longest time constant in the receiver subsystem. In the case of a PLL based clock extraction, this could give a value of the order of 10 000 bits. Taking into account possible limitations of test equipment, a minimum value of 2000 bits is considered acceptable. The content of the pseudo-random section should be generated by a scrambler having the same polynomial as defined in Recommendation G.707. Ideally, the scrambler should "free-run", i.e. the beginning of the pattern should be uncorrelated with the frame alignment section. This arrangement will ensure that the system experiences the worst possible phasing of the pseudo-random binary sequence (PRBS) at some point during the course of the test. However, it is recognized that test equipment limitations may preclude the use of a free running scrambler. Hence it may be necessary to specify a worst-case phasing of the PRBS. This is for further study. The D-period is defined as the first row of the section overhead of the STM-N signal, including valid C1 bytes (consecutive binary numbers) as described in 9.2/G.707. It is recommended that this test be applied to SDH systems at any appropriate point in time during the design or production phase. This would be done to demonstrate the ability of both timing- recovery and decision circuits adequately to handle worst-case SDH signals. It should be emphasized that the test pattern may be rejected by or cause malfunction of certain equipments because, for example, the occurrence of the frame alignment bytes within the pattern. The test should therefore only be used for assemblies not so affected, such as timing-recovery units, receiver amplifier chains, etc. |