CHƯƠNG 3.ENC28J60 – Microchip Stand-Alone Ethernet Controller with SPI Interface

CHƯƠNG 3.ENC28J60 – Microchip Stand-Alone Ethernet Controller with SPI Interface

3.1.Mô tả tổng quan

The ENC28J60 is a stand-alone Ethernet controller with an industry standard Serial Peripheral Interface (SPI). It is designed to serve as an Ethernet network interface for any controller equipped with SPI. The ENC28J60 meets all of the IEEE 802.3 specifications. It incorporates a number of packet filtering schemes to limit incoming packets. It also provides an internal DMA module for fast data throughput and hardware assisted checksum calculation, which is used in various network protocols. Communication with the host controller is implemented via an interrupt pin and the SPI, with clock rates of up to 20 MHz. Two dedicated pins are used for LED link and network activity indication.

ENC28J60 có các thông số sau:

• IEEE 802.3 compatible Ethernet controller

• Integrated MAC and 10BASE-T PHY

• Supports one 10BASE-T port with automatic

polarity detection and correction

• Supports Full and Half-Duplex modes

• Programmable automatic retransmit on collision

• Programmable padding and CRC generation

• Programmable automatic rejection of erroneous

packets

• 8-Kbyte transmit/receive packet dual port SRAM

• Configurable transmit/receive buffer size

• Hardware-managed circular receive FIFO

• Byte-wide random and sequential access with

auto-increment

• Internal DMA for fast data movement

• Hardware assisted

• Supports Unicast, Multicast and Broadcast

Packets

• Two programmable LED outputs for LINK, TX,

RX, collision and full/half-duplex status

• Six interrupt sources and one interrupt output pin

• 25 MHz clock input requirement

• Clock out pin with programmable prescaler

• Operating voltage of 3.1V to 3.6V (3.3V typical)

• 5V tolerant inputs

• Temperature range: -40°C to +85°C Industrial,

0°C to +70°C Commercial (SSOP only)

• 28-pin SPDIP, SSOP, SOIC, QFN packages

3.2.Sơ đồ chân

3.3.Sơ đồ khối

Chip ENC28J60 có bảy khối chức năng chính:

1. An SPI interface that serves as a communication channel between the host controller and the ENC28J60.

2. Control Registers which are used to control and monitor the ENC28J60.

3. A dual port RAM buffer for received and transmitted data packets.

4. An arbiter to control the access to the RAM buffer when requests are made from DMA, transmit and receive blocks.

5. The bus interface that interprets data and commands received via the SPI interface.

6. The MAC (Medium Access Control) module that implements IEEE 802.3 compliant MAC logic.

7. The PHY (Physical Layer) module that encodes and decodes the analog data that is present on the twisted pair interface.

1. Nhóm thanh ghi điều khiển

3.3.1.1.Chức năng của thanh ghi

3.4.Giao tiếp với VĐK

1. Truyền gói

3.4.1.1.Thiết lập việc truyền

3.4.1.2.Tiến trình gởi

3.4.1.3.Trạng thái truyền

1. Nhận gói

Mô hình bus trong mạng CSMA/CD cho phép mỗi nút nhận mọi gói được gởi lên mạng. Bộ lọc nhận sẽ xác định gói nào được phép lưu vào bộ đệm nhận. Không phải mọi gói đều được quan tâm, chỉ có những gói có địa chỉ đích thỏa bộ lọc nhận mới được chuyển vào bộ nhớ. NIC đưa ra một số lựa chọn cho bộ lọc nhận và cách quản lý một gói hoàn chỉnh cho việc lưu trữ gói đang đến.

3.4.1.4.Tiến trình nhận

3.4.1.5.Bộ đệm thu

2. Chuẩn SPI

The ENC28J60 is designed to interface directly with the Serial Peripheral Interface (SPI) port available on many microcontrollers. The implementation used on this device supports SPI mode 0,0 only. In addition, the SPI port requires that SCK be at Idle in a low state; selectable clock polarity is not supported. Commands and data are sent to the device via the SI pin, with data being clocked in on the rising edge of SCK. Data is driven out by the ENC28J60 on the SO line, on the falling edge of SCK. The CS pin must be

held low while any operation is performed and returned high when finished.

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