SÔ ÑOÀ KHOÁI
...........
PHAÀN 3
ÖÙNG DUÏNG
THIEÁT KEÁ MAÏCH COÄNG 8 BIT NHÒ PHAÂN CHO
2 TOAÙN HAÏNG.
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Chöông Trình:
Pheùp coäng 8 bit nhò phaân hai toaùn haïng coù:
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A, B : laø hai toaùn haïng 8bit nhò phaân.
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C(in) – bit nhôù
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S – keát quûa,vaø C(out) –bit daáu.
Coäng 1 bit: caàn 3 ñaàu vaøo : A ,B ,C(in) 2 ñaàu ra laø : S vaø C. Tín hieäu C(out) seõ trôû thaønh C(in) cho laàn coäng keá tieáp..,cöù nhö vaäy , thöïc hieän 8 laàn ta ñöôïc maïch coäng 8 bit nhò phaân cho 2 toaùn haïng.
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-- BOÄ COÄNG MOÄT BIT.
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entity onebit is
port(A,B,Ci : in bit;
S,Co : out bit);
end onebit;
architecture arc of onebit is
begin
S <= A xor (B xor Ci);
Co <= ((A xor B) and Ci ) or (B and A) ;
end arc;
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CAÙCH 1 : SÖÛ DUÏNG PACKAGE.
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package eightbit_package is
component onebit port(A,B,Ci : in bit;
S,Co : out bit);
end component;
end eightbit_package;
library work;
use work.eightbit_package.all;
entity eightbit is
port(A,B : in bit_vector(7 downto 0);
C0 : in bit;
S : out bit_vector(7 downto 0);
C8 : out bit);
end eightbit;
architecture arc of eightbit is
signal C : bit_vector(1 to 7);
begin
g0 : onebit port map(A(0),B(0),C0,S(0),C(1));
g1 : onebit port map( A(1),B(1),C(1),S(1),C(2));
g2 : onebit port map( A(2),B(2),C(2),S(2),C(3));
g3 : onebit port map( A(3),B(3),C(3),S(3),C(4));
g4 : onebit port map( A(4),B(4),C(4),S(4),C(5));
g5 : onebit port map( A(5),B(5),C(5),S(5),C(6));
g6 : onebit port map( A(6),B(6),C(6),S(6),C(7));
g7 : onebit port map( A(7),B(7),C(7),S(7),C8);
end arc;
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CAÙCH 2 : SÖÛ DUÏNG KHAI BAÙO COMPONENT.
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entity eightcom is
port(A,B : in bit_vector(7 downto 0);
C0 : in bit;
S : out bit_vector(7 downto 0);
C8: out bit);
end eightcom ;
architecture arc of eightcom is
component onebit port(A,B,Ci : in bit;
S,Co : out bit);
end component;
signal C : bit_vector(1 to 7);
begin
g1: onebit port map(A(0),B(0),C0,S(0),C(1));
g0tog7 : for i in 1 to 6 generate
g : onebit portp(A(i),B(i),C(i),S(i),C(i+1));
end generate ;
g7 : onebit port map( A(7),B(7),C(7),S(7),C8 );
end arc;
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Chöông Trình Thieát Keá Theo Kieåu Haønh Vi:
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entity FA is
port (A,B : in bit_vector(7 downto 0);
Cin : in bit;
Cout : out bit;
S : out bit_vector(7 downto 0));
end FA ;
architecture data of FA is
begin
process(A,B,Cin)
variable R,C : bit_vector(7 downto 0);
begin
R(0) := A(0) xor B(0) xor Cin;
C(0):= ((A(0) xor B(0)) AND Cin) OR (B(0) AND A(0));
for i in 1 to 7 loop
R(i) := A(i) xor B(i) xor C(i-1);
C(i):=((A(i) xor B(i)) AND C(i-1))OR(B(i) AND A(i));
end loop;
S <= R(7)&R(6)&R(5)&R(4)&R(3)&R(2)&R(1)&R(0);
Cout <= C(7);
end process;
end data;
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